A Design Comparison of Low Power 50 nm Technology Based Inverter with Sleep Transistor and MTCMOS Scheme

ABSTRACT This paper proposes a sleep transistor based minimum size inverter in BSIM4.3.0, 50nm CMOS technology with supply voltage of 1V, power dissipation of 46.28nW at 0.502V and maximum drain current of 70nA. The operating frequency is kept at 1GHz, and found that it can be used up to 10GHz successfully. The reduction in power dissipation is 98.88% and operating frequency is almost 2 times that of classical CMOS inverter. Whereas, the MTCMOS have 37.64nW as max and 56.66nA as max. It is also found better than MTCMOS in terms of delay and maximum power delay product. The trade off is in voltage swing by 15% compared to the conventional CMOS Inverter of the same size. The design is able to satisfy the low standby power requirement and simultaneously high performance during the active mode for many mixed signal applications.